As recent semiconductor memory devices become more integrated, the associated LSI devices become increasingly more compact. The more compact LSI devices require not only a smaller line width, but improved dimensional and positional accuracies of circuit patterns. As a technology to overcome such a problem, a ReRAM (Resistive RAM) is proposed that uses, as a memory, a variable resistance element that reversibly changes the resistance. Then, it is believed that the memory cell array can become more highly integrated by a VAL (Vertical Array Line) structure in the ReRAM that includes the variable resistance element provided between the side walls of word-lines extending in parallel with a substrate and the side walls of bit-lines extending perpendicular to the substrate.
It is required in the VAL structure that thinned interlayer dielectric films are formed between a plurality of stacked word-lines to provide a more integrated memory cell array. However, thinned interlayer dielectric films may reduce the withstand voltage between the memory cells. In this way, it is required in the VAL structure that a more integrated memory cell array is provided while improving the withstand voltage between the memory cells.